1. Field of Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a non-volatile memory and a manufacturing method thereof.
2. Description of Related Art
Among various non-volatile memory products, EEPROM, having the advantages that data can be stored, read, and erased more than once and stored data will not disappear even when power is cut off, has become a memory device widely used in personal computers and electronic equipment.
A conventional EEPROM has a floating gate and a control gate, which are manufactured by doped polysilicon. In order to prevent a false determination caused by over-erasing or over-writing when the conventional EEPROM is erasing or writing, a select transistor is connected in series on one side of the floating gate and the control gate, such that programming and reading of the memory can be controlled by the transistor.
In the operation of the EEPROM, generally speaking, the greater the gate-coupling ratio (GCR) between the floating gate and the control gate, the lower the working voltage for the operation, such that the operational speed and efficiency of the memory are greatly enhanced. Since the GCR indicates the ratio of the capacitance value between the floating gate and the control gate to the total capacitance value of the memory, therefore, the increase of the equivalent capacity area between the floating gate and the control gate helps to increase the GCR.
However, along with the trend of high integrity of integrated circuits, the area occupied by each memory cell of the memory must be reduced, and then the linewidth of a device is also reduced accordingly. As such, the GCR between the floating gate and the control gate is decreased, such that the working voltage required by the non-volatile memory must be increased, which negatively affects the non-volatile memory applied in the field of portable electronic products requiring low energy consumption. Therefore, it is an important topic to manufacture a memory with high GCR in a limited chip area.